LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY im_double IS
    PORT (
        in_c  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
        out_c : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
        exop  : IN  STD_LOGIC
    );
END im_double;

ARCHITECTURE behav OF im_double IS
BEGIN
    PROCESS(in_c, exop)
    BEGIN
        CASE exop IS
            WHEN '0' =>
               out_c<= (others => '0');  -- 无符号扩展
					out_c(7 downto 0) <= in_c;  
            WHEN '1' =>
                out_c <= (others => in_c(7)); -- 有符号扩展
					 out_c(7 downto 0) <= in_c; 
        END CASE;
    END PROCESS;
END behav;